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Integrated Device Technology, Inc.
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
DESCRIPTION:
IDT54/74FCT161T/AT/CT IDT54/74FCT163T/AT/CT
FEATURES:
* * * * Std., A and C speed grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, QSOP, CERPACK and LCC packages
* * * * *
The IDT54/74FCT161T/163T, IDT54/74FCT161AT/ 163AT and IDT54/74FCT161CT/163CT are high-speed synchronous modulo-16 binary counters built using an advanced dual metal CMOS technology. They are synchronously presettable for application in programmable dividers and have two types of count enable inputs plus a terminal count output for versatility in forming synchronous multi-stage counters. The IDT54/74FCT161T/AT/CT have asynchronous Master Reset inputs that override all other inputs and force the outputs LOW. The IDT54/74FCT163T/AT/CT have Synchronous Reset inputs that override counting and parallel loading and allow the outputs to be simultaneously reset on the rising edge of the clock.
FUNCTIONAL BLOCK DIAGRAMS
P0 PE '161 '163 CEP CET 163 ONLY TC P1 P2 P3
CP
CP
161 ONLY
CP
D CP D CD QQ Q0 Q0 DETAIL A MR ('161) SR ('163) Q0 Q1 Q2 Q3
2611 drw 01
DETAIL A
DETAIL A
DETAIL A
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
OCTOBER 1994
DSC-4219/4
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IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS IDT54/74FCT861 10-BIT TRANSCEIVERS
*R CP P0 P1 P2 P3 CEP GND
1 2 3 4 5 6 7 8 16
INDEX
P16-1, D16-1, S016-1, S016-7 & E16-1
15 14 13 12 11 10 9
CEP GND NC PE CET
Vcc TC Q0 Q1 Q2 Q3 CET PE
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CP *R NC Vcc TC
3 2 1 4 5 6 7 8 20 19 18 17 16 15 14 9 10 11 12 13
P0 P1 NC P2 P3
L20-2
Q0 Q1 NC Q2 Q3
2611 drw 03
*MR for '161 *SR for `163
DIP/SOIC/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
PIN DESCRIPTION
Pin Names CEP CET CP Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Parallel Data Inputs Parallel Enable Input (Active LOW) Flip-Flop Outputs Terminal Count Output
2611 tbl 01
FUNCTION TABLE(2)
SR(1)
L H H H H
PE
X L H H H
CET X X H L X
CEP X X H X L
Action on the Rising Clock Edge(s) Reset (Clear) Load (PnQn) Count (Increment) No Change (Hold) No Change (Hold)
MR (`161) SR (`163)
P0-3
PE
Q0-3 TC
2611 tbl 02 NOTES: 1. 163 only. 2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial VTERM(2) Terminal Voltage -0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage -0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature -55 to +125 Under Bias TSTG Storage -55 to +125 Temperature PT Power Dissipation 0.5 IOUT DC Output Current -60 to +120 Military -0.5 to +7.0 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
2611 lnk 04
-0.5 to VCC +0.5 -55 to +125 -65 to +135 -65 to +150 0.5 -60 to +120
V C C C W mA
NOTE: 1. This parameter is measured at characterization but not tested.
2611 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
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IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL II VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) Input HIGH Current
(4)
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max., VI = VCC (Max.) VCC = Min., IN = -18mA VCC = Max. , VO = GND VCC = Min. VIN = VIH or VIL IOH = -6mA MIL. IOH = -8mA COM'L. IOH = -12mA MIL. IOH = -15mA COM'L.
(3)
Min. COM'L MIL
(5)
Typ.(2) -- -- -- -- -- -- -0.7 -120 3.3 3.0 0.3 200 0.01
Max. -- -- 0.8 1 1 1 -1.2 -225 -- -- 0.5 -- 1
Unit V V V A A A V mA V V V mV mA
2611 tbl 05
2.0V 2.7V -- -- -- -- -- -60 2.4 2.0 -- -- --
VI = 2.7V VI = 0.5V
Clamp Diode Voltage Short Circuit Current Output HIGH Voltage
VOL VH ICC
Output LOW Voltage Input Hysteresis Quiescent Power Supply Current
VCC = Min. VIN = VIH or VIL -- VCC = Max. VIN = GND or VCC
IOL= 32mA MIL. IOL= 48mA COM'L.
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. Clock pin requires a minimum VIH of 2.5V.
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IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max., Outputs Open Load Mode CEP = CET = PE = GND MR or SR = VCC One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open Load Mode fCP = 10MHz 50% Duty Cycle CEP = CET = PE = GND MR or SR = VCC One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max., Outputs Open Load Mode fCP = 10MHz 50% Duty Cycle CEP = CET = PE = GND MR or SR = VCC Four Bits Toggling at fi = 5MHz 50% Duty Cycle VIN = VCC VIN = GND Min. -- -- Typ.(2) 0.5 0.15 Max. 2.0 0.25 Unit mA mA/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
1.5
3.5
mA
VIN = 3.4V VIN = GND
--
2.0
5.5
VIN = VCC VIN = GND
--
3.8
7.3(5)
VIN = 3.4V VIN = GND
--
5.0
12.3(5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
2611 tbl 06
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IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT161T IDT54/74FCT163T Com'l. Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL tSU Parameter Propagation Delay CP to Qn (PE Input HIGH) Propagation Delay CP to Qn (PE Input LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay MR to Qn ('161) Propagation Delay MR to TC ('161) Set-up Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Set-up Time, HIGH or LOW PE or SR to CP Hold Time, HIGH or LOW PE or SR to CP Set-up Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Clock Pulse Width (Load) HIGH or LOW Clock Pulse Width (Count) HIGH or LOW Condition(1) CL = 50pF RL = 500 2.0 11.0 2.0 Mil. 11.5 IDT54/74FCT161AT IDT54/74FCT163AT Com'l. 2.0 7.2 2.0 Mil. 7.5 IDT54/74FCT161CT IDT54/74FCT163CT Com'l 2.0 5.8 2.0 Mil. Unit ns 6.3
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
2.0
9.5
2.0
10.0
2.0
6.2
2.0
6.5
2.0
5.8
2.0
6.3
ns
2.0 1.5 2.0 2.0 5.0
15.0 8.5 13.0 11.5 --
2.0 1.5 2.0 2.0 5.5
16.5 9.0 14.0 12.5 --
2.0 1.5 2.0 2.0 4.0
9.8 5.5 8.5 7.5 --
2.0 1.5 2.0 2.0 4.5
10.8 5.9 9.1 8.2 --
2.0 1.5 2.0 2.0 4.0
7.4 5.2 6.0 7.0 --
2.0 1.5 2.0 2.0 4.5
8.3 5.6 6.6 7.7 --
ns ns ns ns ns
tH
1.5
--
2.0
--
1.5
--
2.0
--
1.5
--
2.0
--
ns
tSU
11.5
--
13.5
--
9.5
--
11.5
--
9.5
--
11.5
--
ns
tH
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
1.5
--
ns
tSU
11.5
--
13.0
--
9.5
--
11.0
--
9.5
--
11.0
--
ns
tH
0
--
0
--
0
--
0
--
0
--
0
--
ns
tW
5.0
--
5.0
--
4.0(3)
--
4.0(3)
--
4.0(3)
--
4.0(3)
--
ns
tW
7.0
--
8.0
--
6.0
--
7.0
--
6.0
--
7.0
--
ns
tW tREM
MR Pulse Width, LOW ('161)
Recovery Time MR to CP ('161)
5.0 6.0
-- --
5.0 6.0
-- --
4.0(3) 5.0
-- --
4.0(3) 5.0
-- --
4.0(3) 5.0
-- --
4.0(3) 5.0
-- --
ns ns
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This limit is guaranteed but not tested.
2611 tbl 07
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IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL
2611 drw 04
SWITCH POSITION
Test
7.0V
Switch
Open Drain Disable Low Enable Low All Other Tests
Closed Open
VOUT
500
2611 lnk 08 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2611 drw 05
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2611 drw 06
tSU
tH
PROPAGATION DELAY
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2611 drw 07
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ 0.3V VOH 0V
2611 drw 08
DISABLE 3V 1.5V 0V 3.5V 0.3V VOL
tPLZ
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT X FCT X Family XXXX Device Type X Package X Process
Temperature Range
Blank B P D L SO E Q 161T 163T 161AT 163AT Blank 54 74
Commercial MIL-STD-883, Class B Plastic DIP CERDIP Leadless Chip Carrier Small Outline IC CERPACK Quarter-size Small Outline Package Synchronous Binary Counter with Asynchronous Master Reset
High Drive -55C to +125C 0 to +70C
2611 drw 09
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